VFX 7 - Hardware description

VFX Article, Chapter 7

7. Hardware description

The hardware for the VFX processor is relatively simple. The schematic diagram is shown in Figure 6. The ADSP-2105 (U1) is the DSP microprocessor. It has 1k x 24 bit words of fast program memory (PM) on board. On power-up and after a reset the 2105 boots the program from the EPROM (U2) into this on-board memory. The boot function is built into the 2105 and it allows a slower and inexpensive EPROM (250 ns) to supply the 1k words (3k bytes) of PM. The Boot Memory Select (BMS) output of the 2105 selects the EPROM and the addressing is automatically generated on the external address bus. The selection of the program booted can be programmed by the 2105, however to simplify the VFX hardware and software, the program is selected by setting the three MSB's of the EPROM's address with dip switch S1.

In addition to the on-board PM there is .5k x 16 bit words of on board Data Memory (DM). Since this is not enough to perform the 128 point FFT and IFFT two external static RAMS are also attached to the data bus, one for the HI byte (U9) and one for the LO byte (U8) of the memory. This 2 X 8k bytes of SRAM addressed by the 2105 is accessed when the Data Memory Select (DMS) strobe is active. The seven segment LED display adds to the interactivity of the VFX processor and is written to as if it was external program memory. The Program Memory Select (PMS) signal from the 2105 is activated to latch the data bus in the seven segment BCD latch/decoder/driver. The driver then drives the seven segment display. No decoding is required for the selection of the seven segment latch/decoder/driver since there is no external program memory in the system.

The 2105 has a built in oscillator that requires a 10 Mhz crystal and two small capacitors to operate. The VFX processor uses a CODEC (CODe-DECode) to digitize the audio input and convert it into a serial data stream. The CODEC interfaces directly with the 2105's synchronous serial port SPORT1. SPORT1 is configured for 8 bit synchronous data transfer with word framing sync pulses and u-Law companding. The 2105 generates a 1.66 Mhz serial clock SCLK1 and 6.5 khz framing pulses on Transmit Frame Sync (TFS1) and Receive Frame Sync (RFS1) to synchronize the data transfer. The CODEC implements u-law companding whereby the dynamic range of the conversion is improved by taking advantage of human perception of sound; that is, that the ear is much more sensitive to noise in low level (volume) signals than in high level signals. The CODEC receives and transmits 8 bits of data and the 2105 has built in hardware companding to convert it into a 14 bit number. The 2105 serial port can also implement A-law companding which is a different standard but serves the same purpose.

The other components of the VFX processor are the power supply and analog components. The VFX board accepts 9 VDC and generates the following supply voltages: -9 VDC, +5 VDC logic, +5.1 VDC analog and -5.1 VDC analog. The voltage converter (U7-TSC7660) generates the negative supply. A simple three terminal 5 VDC regulator supplies +5 VDC power to the 2105 and logic. Two zener regulators (CR1 and CR2) generate the analog power supply voltages of +5.1 and -5.1 VDC. U4 and U5 condition and amplify the audio input and output respectively.