VFX Article, Chapter 2

2. Hardware Architecture

The architecture for the VFX processor is straightforward as shown in Figure 1. It consists of a microphone input circuit utilizing a National Semiconductor TP3054 CODEC, the Analog Devices ADSP-2105 DSP chip, an 8k X 8 EPROM, two 8K X 8 SRAM chips, power supply circuitry and audio conditioning. The CODEC incorporates an input anti-aliasing filter, the A/D converter, the D/A converter and output filter along with control circuitry. The 2105 interfaces to the CODEC via serial interface SPORT1 (See Figure 6). The SRAMs provide 8K x 16 bit words of data storage to supplement the 2105's internal 512 words. The 2105 accesses them using the Read and Write signals and the Data Memory Select (DMS). The 2105 can access external memory in 100 nsec but has an internal wait state generator to allow the use of slower devices. The VFX processor has 3 wait states programmed for external data memory accesses. The VFX processor performs four functions, the theory of operation for each in hardware is virtually identical. The software makes the hardware perform these multiple effects. The algorithms for each effect is described below. Section 7 describes the hardware in detail below.

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